The present invention relates to a multi-stage high-frequency power amplifier circuit with a plurality of cascaded semiconductor amplifier devices and technology that is useful when applied to wireless communication devices such as cellular phones incorporating a high-frequency power amplifier circuit, and more particularly to a high-frequency power amplifier circuit capable of obtaining output with desired characteristics, independent of variations in semiconductor amplifier device characteristics.
The transmission output stage of car phones, cellular phones, and other wireless communication devices (mobile communication devices), as shown in FIG. 1, includes a multi-stage high-frequency power amplifier circuit with cascaded semiconductor amplifier devices Q1, Q2, and Q3 made of MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), GaAs-MESFETs (Metal Semiconductor Field-Effect Transistors), or other applicable kinds of transistors. The high-frequency power amplifier circuit shown in FIG. 1 generally includes a discrete last-stage semiconductor amplifier device Q3 (such as an output power MOSFET), and preceding-stage semiconductor amplifier devices Q1 and Q2 and a bias circuit BIAS that are integrated onto a single semiconductor chip as a semiconductor integrated circuit. The combination of this discrete semiconductor amplifier device part and a semiconductor integrated circuit including a bias circuit, together with capacitive elements and other circuit elements will be referred to as a high-frequency power amplifier module or just as a module hereinafter.
In general, a cellular phone system is configured to change its output (transmission power) in different communication environments according to power-level command signals from a base station, so as not to interfere with other cellular phones. For example, a high-frequency power amplifier module in the transmission output stage of cellular phones adopting the U.S. 900-MHz band standard system or the European GSM (Global System for Mobile Communications) system is configured so that the gate bias voltages of the output power MOSFETs Q1 to Q3 are controlled by the output voltage Vapc of an Automatic Power Control (APC) to produce the output power required for communication.
Conventionally, the gate bias voltages of the output power MOSFETs are generated by using a bias circuit BIAS consisting of resistance dividers as shown in FIG. 1, in which the output voltage Vapc of the APC circuit is divided by the ratios of paired resistances R11 and R12, R21 and R22, and R31 and R32 to generate gate bias voltages Vg1, Vg2, and Vg3 (see, for example, Unexamined Japanese Patent Publication No. Hei 11(1999)-150483).
Some conventional systems, as shown in FIG. 2, use a bias circuit that is configured with a plurality of resistances R1 to R4 connected in series with a MOSFET Qd that functions as a diode, forming a resistive voltage in which the ratio of the resistance values is adjusted so that the maximum output power can be obtained when Vapc is in the high neighborhood of 2 V, generating the gate bias voltages Vg1, Vg2, and Vg3 of the output power MOSFETs in each stage (see, for example, Unexamined Japanese Patent Publication No. 2001-102881).
As described above, all of the conventional gate bias circuits above apply bias voltages generated by dividing the output voltage Vapc of the APC circuit to the gates of the output power MOSFETs.